Integrated circuits are fabricated by forming a layer, performing some type of processing in regard to that formed layer—such as etching—and then forming an overlying layer. This process is repeated many times until the completed integrated circuit is formed.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
It is often very desirable to know certain properties of a given layer within an integrated circuit. However, some layers do not adopt their final properties until other layers are formed on top of them, or they are otherwise unavailable for convenient measurement until they are buried underneath the subsequently formed layers.
One example of such a layer is the gate insulation layer. The gate insulation layer is traditionally formed of a very thin silicon oxide layer, or more recently of a very thin high k layer, such as oxides of heavy and rare earth metals having higher dielectric constants and higher capacitances, such as HfSiON, ZrO2, ZrSiON, HfO2, HfON, La2O3, CeO2, Na2O3, Sm2O3, Eu2O3, Gd2O3, Tb2O3, Dy2O3, HO2O3, Er2O3, Tm2O3, Yb2O3, and Lu2O3.
The existing methods to measure gate insulation layers are predominantly optical techniques, ellipsometry, XPS, and X-ray-electron spectroscopy. These techniques suffer from various drawbacks. For example, some require a relatively large measurement spot size, and are therefore used on monitor substrates only because they are not appropriate for production substrates, which have very small features. Further, some of these techniques are used on exposed gate insulation layers. When the gate insulation layer is capped with the gate electrode layer, these measurement techniques are not able to measure the underlying gate insulation layer.
Another possible method is to use an electron probe micro analysis technique, which can penetrate down through the gate electrode layer to the gate insulation layer. However, in this case the measurement of the gate insulation layer is confounded by a native oxide layer that forms on the top surface of the gate electrode layer, and which in many instances will have a comparable thickness.
Unfortunately, the native oxide thickness is generally unknown, and tends to be relatively non-uniform both across the substrate and from substrate to substrate. Not knowing the thickness of the native oxide introduces a large variation and inaccuracy into the measurement of an extremely thin gate insulation layer.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.